Tool Demo 1

The First Public “SNEAK PEAK” at DSLGen, a platform independent program generation system that produces optimized code (without reprogramming) for multiple platform architectures. The target computation is specified in a programming language independent form and need not ever be changed unless the target computation changes. The target platform architecture is specified separately in terms of high level domain specific descriptors. Only the platform specification needs to change when moving to a new platform.

The demonstration version of the system is implemented for the following platform architectures: Simple Von Neumann machine, a multicore with threads machine, a vector machine (i.e., Intel’s SSE instruction set) and a combination of multicore and vector. Other architectures envisioned are: GPU (producing CUDA) , FPGA, DSP (Digital Signal Processor) platform, and others.

DSLGen is written in CommonLisp and CLOS (CommonLisp Object System).

The demonstration will drill into the PATENTED technology underlying DSLGen. It will examine the fundamentally new representation system used (constraint based) and the tools that operate on that representation. We will walk through an example generation and introduce the tools along the way.

The Walk Through:

  1. Generated Code Examples

  2. Phased Generation

    1. Building the logical architecture (LA), e.g., partitioning constraints

    2. Adapting the LA by adding design features, e.g., re-partitioning with synthetic partitions

    3. Mapping the LA to the Physical Architecture (PA)

      1. Instantiating a design framework by cloning and specialization

    4. Simplification with partial evaluation and some inference

  3. Performance Results

Tools and Technologies Used:

  1. Transformations (Regular and “Method Transformations”)

    1. What does a transformation look like?

    2. The Pattern Language and Matcher

  2. Partial evaluation system for program simplification

    1. Inference subsystems (Inequality Solver/Checker)

  3. Type Inference Subsystem

  4. History debugger for Domain Engineers who are extending DSLGen to new domains or execution platforms

    1. Searching the history and Bookmarking

  5. Logical Architecture Browser for examining Planned program architecture before conversion into programming language form

    1. Loop and Partition Constraints

    2. Design feature encapsulation via specializations

This will be the ONLY VENUE (for a year or more) where this information is presented.